Configuration access mechanism for packet switching architecture

ABSTRACT

A method for accessing a configuration space of a device is described. The method includes setting a first field of a packet to a value to specify a destination device, and setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet. The method further includes setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device, and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.

RELATED APPLICATION

This application claims the benefit of the earlier filing date of co-pending U.S. Provisional Patent Application No. 60/493,113, filed Aug. 4, 2003, currently pending.

BACKGROUND

1. Field

Embodiments of the invention relate to the field of computer systems, and more specifically, to the field of device configuration for computer systems.

2. Background

Devices and subsystems of a computer system may have configuration registers that may be accessed or programmed prior to or during the operation of the computer system. Conventional computer systems typically implements configuration registers that have limited space. For example, conventional Peripheral Component Interconnect (PCI) architecture limits a configuration register space available on a given device to, for example, 256 bytes. PCI Express Base architecture, as defined in a PCI Express Base Specification Revision 1.0 dated Jul. 22, 2002 by the PCI-SIG (Peripheral Component Interconnect—Special Interest Group), extended the available configuration register space of a given device to 4 kilobytes. Even with an increased configuration space of up to 4 kilobytes, Advanced Switching (AS) architecture requires more scalability especially when dealing with multi-ported switch devices given PCI Express-AS uni-function device configuration model. As a result, the configuration register space limitation burdens PCI and PCI Express Base architecture.

Additionally in PCI and PCI Express Base architecture there is, in many cases, potentially a necessary split between configuration mechanism that must be used to work around the configuration space limitations mentioned above. For example PCI and PCI Express Base components, if needed, must request additional internal configuration register, or table space by requesting a memory, or I/O (input/output) mapped space. As a result, to fully configure a PCI or PCI Express Base component of this type, some of the component set up may require using configuration transactions, while other elements may require set up using either memory or I/O transactions.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is illustrated by way of example and not by way of limitation in the Figures of the accompanying drawings in which like references indicate similar elements. It should be noted that the references to an or one embodiment of this disclosure are not necessarily to the same embodiment, and such references mean at least one.

FIG. 1 illustrates a block diagram of one embodiment of a computer system in which the invention may be implemented.

FIG. 2 illustrates a configuration space of a device according to one embodiment.

FIG. 3 illustrates a simplified representation of a configuration packet according to one embodiment.

FIG. 4 illustrates a configuration read packet header according to one embodiment.

FIGS. 5A and 5B illustrate configuration read completion packet headers according to one embodiment.

FIG. 6 illustrates a configuration write packet header according to one embodiment.

DETAILED DESCRIPTION

In the following description, specific details are set forth. However, it is understood that embodiments may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail to avoid obscuring the understanding of this description.

FIG. 1 illustrates one embodiment of computer system 100 in which the invention may be implemented. System 100 includes processor 101, processor bus 146, memory controller 104 and main memory 106. Processor 101 may comprise any suitable processor, such as a processor from the Pentium

family of processors available from Intel Corporation of Santa Clara, Calif. Alternatively, other processors may be used. System 100 may include one or more processors. Although described in the context of system 100, embodiments of the invention may be implemented in any suitable computer system comprising any suitable combination of integrated circuits.

Also included in system 100 is host bridge 102 coupled to processor bus 146 and switch fabric 110. Host bridge 102 may include any suitable interface controllers to provide for any suitable communication link to processor bus 146 and/or the devices coupled via switch fabric 110. In one embodiment, switch fabric 110 is Advanced Switching (AS) fabric having features for PCI Express Base architecture, as defined by PCI Express Base specification. Switch fabric 110 includes one or more switches 112, 114, which control data path between various devices of the computer system. Each switch may include a number of ports, each port capable of connecting to another switch or a device within the system or network.

A number of devices may be connected to the switches 112, 114 via fibers (or links). A fiber is a bi-directional communication path between two connect points (e.g., switches and endpoint devices) in a computer system or network. In the illustrated system 100, fabric 110 includes a first switch 112 coupled to host bridge 102, device(1) 116, device(4) 118, device(3) 120 and switch 114 via five separate switching fibers 138, 140, 142, 144, 134, respectively. The second switch 114 is coupled to switch 112 and device(2) 122 via two separate switching fibers 134, 136, respectively. Devices(1)-(4) may be processing elements or may be any device from which a transaction originates or terminates.

For one embodiment, configuration access packets may be transferred between any two suitable devices of system 100. For example, system 100 may enable a requesting device, such as processor 101 to generate and transmit a configuration access packet to any one of devices (1)-(4), etc via switches 112 and 114. The configuration access packet may be used by a requesting device to gain access to a configuration space of a destination device.

FIG. 2 illustrates configuration space 200 of a device according to one embodiment. The device implementing the configuration space may be any device incorporated within a computer system or network, such as, for example, microprocessor, storage device, input/output (I/O) device, switch. Configuration space 200 is divided into a number of configuration files 205, 210 and 215 referred to as Local Resource Files (LRFs). The terms file and LRF in this context are used to described a block of memory that enables a device to distinguish one set of information from another.

In accordance with one embodiment, configuration space 200 of a device may be organized in a number of different ways. Additionally, each device may segregate information into different configuration files (e.g., LRFs) in a number of different ways. According to one embodiment, each LRF may vary in memory size. In one implementation, the configuration space is organized such that each LRF can be expanded up to four gigabytes in memory size.

As shown in FIG. 2, the illustrated configuration space 200 includes a number of configuration files (LRFs), which are indexed as LRF(0) through LRF(N). In one implementation, configuration space 200 of a device may define up to sixteen LRFs. It should be understood that the number of configuration files (LRFs) included in a configuration space is an implementation choice and could be any number of LRFs (e.g, 2, 4, 8, 32, etc).

In should be noted that such configuration space arrangement using a configuration space divided into a number of separate files (LRFs) provides a scalable configuration space, in which each separate configuration file (LRF) may be accessed using index scheme. Such configuration space arrangement eliminates a fundamental configuration register space limitation that burdens PCI and PCI Express Base architecture implementations.

As shown in FIG. 2, configuration files (LRFs 205, 210 and 215) may have entries 220, 225, 230 associated with pointers 240, 245 that point to a particular location within the same LRF or a particular location within other LRFs. The location pointed to by the pointer may contain various information relating to a given device (e.g., functionality and/or capabilities of the device).

In one embodiment, a configuration space of a device is set up such that the first configuration file is indexed LRF(0). LRF(0) may contain basic information (e.g., configuration settings, functionality and/or capabilities of the device) about the device and may also contain information necessary for understanding how the remaining portion of the configuration space is organized. Accordingly, if a device, such as a processor, is trying to identify what kinds of devices are attached to the switch fabric, the processor can access LRF(0) of each of the attached devices to obtain basic information about the attached devices and to figure out how the remaining portion of the configuration space is organized.

In accordance with one embodiment, a configuration space of a device may be set up such that it can restrict access on a LRF-by-LRF basis. Access rights may be assigned to enable other devices to access the configuration space on a LRF-by-LRF basis. By assigning access rights to each individual LRF, the system can control which device has access to each LRF and which device has the ability to alter the information contained in each LRF. For example, the configuration space may be configured such that a set of devices can read the entire configuration space while another set of devices can only read certain files of the configuration space. Additionally, the configuration space may be configured such that some devices can read from the entire configuration space but can only write to a portion of the configuration space.

FIG. 3 illustrates a simplified representation of packet 300, according to one embodiment, transmitted from one device to another via a switch fabric. Packet 300 may include routing header 305, configuration packet header 310 and data payload 315. In one embodiment, routing header 305 includes, among other things, destination address field 325 to identify the destination device and packet type field 320 that indicates the type of packet. For example, when packet type field 320 is encoded as a certain value (e.g., 4), this indicates that the packet is formatted for access to a configuration space of a destination device. Accordingly, when packet type field 320 is encoded as the value (e.g., 4), the packet will be used by the destination device to enable access to its configuration space.

More specifically, when a packet has reached its destination, the destination device will examine a second header 310 immediately following routing header 305 to determine what is being requested by packet 300. When the packet indicates that it is of configuration access type designated by the packet type field, the header immediately following routing header 305 will be configuration packet header 310 formatted to access a configuration space of a destination device.

As shown in FIG. 3, configuration packet header 310 includes, among other things, transaction type field 330 that indicates what type of transaction (e.g., read request, read completion and write request) is being requested by the packet. Additionally, configuration packet header 310 includes, LRF index 335 field, which is used to specify which one of the LRFs within the configuration space of the destination device, and address field 340 (e.g., 32-bit), which is used to point to a specific memory location within the specified LRF.

If transaction type field 330 indicates that the packet is a configuration write request, the destination device may take data payload 315 and write to a specific configuration file specified by LRF index 335 and to a specific location within the configuration space specified by address field 340. If transaction type field 330 indicates that the packet is a configuration read request, the destination device may generate a read completion packet to return the data specified by LRF index 335 and a specific location within the configuration space specified by the value set in address field 340.

Configuration access packets for accessing a configuration space of a given device are described in more detail with reference to FIGS. 4-6. In one embodiment, configuration access packets are used to access a configuration space that is divided into a number of segregated files. In the embodiment shown in FIGS. 4-6, configuration access packets include 4-bit field to access up to sixteen different LRFs of a given device. Additionally, in the embodiment shown in FIGS. 4-6, configuration access packets includes 32-bit address field to reference up to 4 gigabytes of configuration space with a given LRF.

In accordance with one embodiment, by providing a configuration space with a number of segregated files, each file accessed using 32-bit addressing, the configuration access mechanism provides an access to a relatively large amount of configuration space that a requesting device can address.

In one embodiment, read requests are transferred between two devices using a split transaction protocol. For split transaction protocol, there are two types of read packets: read request packet and read completion packet. Read request packets are used to initiate read transactions. Read completion packets are used to return read data. Read completion packets are associated with their corresponding read request packets by transaction numbers. In one embodiment, because PEI 4 is defined as a memory mapped load/store transport service there are no responses to configuration write packets.

FIG. 4 illustrates a format for a configuration read request packet header according to one embodiment. In one embodiment, the illustrated read request packet header is used to read information from configuration space of Advanced Switching (AS) device. In the illustrated embodiment, the configuration read request packet header is one double-word. The fields of the configuration read request packet header, shown in FIG. 4, are described in Table 1. TABLE 1 Configuration Read Request Packet Header Fields Field Name Description Type This field indicates the type of packet. Read request packets are identified with a 0, read completion packets with a 1, and write request packets with a 2 and sequenced write request packets with a 3 in this location. Offset [31:2] This field provides the offset (address) of the requested data relative to LRF Page Index. LRF Page Index This field indicates the LRF Page Index for the associated access. Transaction Number This field indicates the requested specific identifier for the request. This field is used to match request with completions. CRC This bit indicates whether the associated packet is protected by a Cyclic Redundancy Check Flag (CRC) value. When set, there is an additional double word of CRC appended to the encapsulated packet. When clear, the encapsulated packet ends immediately after the 8- byte header. Dwords Requested This field indicates the number of double words requested by the requester. The number of double words requested is the maximum number of double words that the read target is allowed to return in response to the request. The read target may return fewer than the requested number of double words. The byte disable masks (i.e., First Dword Byte Disable Mask and Last Dword Byte Disable Mask) may be used to affect a partial double word access. First Dword This field defines which bytes of the first double word of the Byte Disable Mask requested data are enabled (e.g., associated bit in mask is clear) and which bytes are disabled (e.g., corresponding bit is set). Last Dword This field defines which bytes of the last double word of the Byte Disable Mask requested data are enabled (e.g., associated bit in mask is clear) and which bytes are disabled (e.g., corresponding bit is set).

FIGS. 5A and 5B illustrate a format for configuration read completion packet headers according to one embodiment. In one embodiment, the read completion packet headers are used to read information from configuration space of Advanced Switching (AS) device. In the illustrated embodiment, the configuration read completion packet headers are each one word.

In accordance with one embodiment, there are two different types of configuration read completion packet headers. When the configuration read is successful, the termination type field (TTF) will indicate that no errors were encountered (e.g., bit is clear). In this case, the configuration read completion packet will contain read data that is returned from the destination device to the requesting device. And the number of double-words contained in the packet s payload may be determined by examining the payload dwords field, as shown in FIG. 5A. When the configuration read in unsuccessful, the termination type field (TTF) will indicate that errors were encountered during read sequence (e.g., bit is set). In this case the completion status field will contain some other value that is not related to payload size, as shown in FIG. 5B. The fields of the configuration read completion packet headers, shown in FIGS. 5A and 5B, are described in more detail in Table 2. TABLE 2 Configuration Read Completion Packet Header Fields Field Name Description Type This field indicates the type of packet. Read request packets are identified with a 0, read completion packets with a 1, and write request packets with a 2 and sequenced write request packets with a 3 in this location. LRF Page Index This field indicates the LRF Page Index for the associated access. Transaction Number This field indicates the requested specific identifier for the request. This field is used to match request with completions. CRC This bit indicates whether the associated packet is protected by a Cyclic Redundancy Check Flag (CRC) value. When set, there is an additional double word of CRC appended to the encapsulated packet. When clear, the encapsulated packet ends immediately after the 8-byte header Payload Dwords (Shown This field indicates the number of double words in the packet s in FIG. 4A) payload. Completion Status This field indicates the termination status of an abnormally (Shown in FIG. 4B) terminated sequence. Following are the completion status and their meanings: 0 = No Data (not an error) 1 = LRF Page Index Access Error 2 = Target Abort 3 = Master Abort 4 = Time Out 5 = Lock Out

FIG. 6 illustrates a format for a configuration write packet header according to one embodiment. In one embodiment, the write packet header is used to configure Advanced Switching (AS) device. In the illustrated embodiment, the configuration write packet header is one double-word. For write type requests, the configuration access packet may have associated data attached to the configuration write packet header. The fields of the configuration write packet header, shown in FIG. 6, are described in Table 3. TABLE 3 Configuration Write Packet Header Fields Field Name Description Type This field indicates the type of packet. Read request packets are identified with a 0, read completion packets with a 1, and write request packets with a 2 and sequenced write request packets with a 3 in this location. Offset [31:2] This field provides the offset (address) of the associated data payload relative to LRF Page Index. LRF Page Index This field indicates the LRF Page Index for the associated write. Transaction Number Transaction number 0 indicates that the write packet is a self- contained transaction. That is, it is not part of a sequenced write. A non-zero transaction number indicates that this packet is the first in a series of write transactions (sequenced write). CRC This bit indicates whether the associated packet is protected by a Cyclic Redundancy Check Flag (CRC) value. When set, there is an additional double word of CRC appended to the encapsulated packet. When clear, the encapsulated packet ends immediately after the 8- byte header Payload Dwords This field indicates the number of double words of payload being written. A Payload Dwords value of 0 is interpreted as a zero byte write. A zero dword write requires that the write target perform its normal pipe and range accesses, but does not require that any remote data write be performed. By contrast, another form of zero byte write is possible by supplying one or two double words of data and byte masking all the bytes within the double word data. The latter form of zero byte write does require that the associated address(es) and byte masked data be played out to the remote system. First Dword This field defines which bytes of the first double word of the supplied Byte Disable Mask write data are enabled (e.g., associated bit in mask is clear) and which bytes are disabled (e.g., corresponding bit is set). Last Dword This field defines which bytes of the last double word of the supplied Byte Disable Mask write data are enabled (e.g., associated bit in mask is clear) and which bytes are disabled (e.g., corresponding bit is set).

FIGS. 4-6 illustrates an exemplary configuration access packet header using (1) 4-bit indexing to enable selection of up to sixteen configuration files specified by the value set in the LRF index field, and (2) 32-bit addressing to address a specific memory location within the selected file specified by the value set in the offset (address) field. It should be understood that embodiments of the invention can be implemented with different LRF index field size and different offset (address) field size.

In operation, a requesting device, such as a processor may initiate a configuration access packet by encoding various information in a suitable format as specified in Tables 1-3. The configuration access packet may be generated by (1) setting a destination address field, in the routing header of the packet, to a value in order to specify the destination device, (2) setting a packet type field, in the routing header of the packet, to a defined value to indicate that the packet is a configuration access packet, (3) setting a LRF index field, in the configuration packet header, to select one of configuration files of a configuration space of the destination device, and (4) setting an address field, in the configuration packet header, to address a specific memory location within the selected configuration file. Once the requesting device has generated the configuration access packet, the configuration access packet is transferred from the requesting device to the destination device via buses and/or switch fiber.

While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting. 

1. A method comprising: setting a first field of a packet to a value to specify a destination device; setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet; setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device; and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.
 2. The method of claim 1, further comprising transmitting the configuration access packet from a requesting device to the destination device specified by the value set in the first field of the configuration access packet.
 3. The method of claim 2, further comprising: receiving the configuration access packet; determining which one of the apertures of the configuration space is being selected by the configuration access packet; and determining a specific address within the selected aperture being accessed by the configuration access packet.
 4. The method of claim 1, wherein the third field is specified using a 4-bit indexing to enable selection of up to sixteen configuration apertures of the destination device.
 5. The method of claim 1, wherein the fourth field is specified using 32-bit addressing to address up to four gigabytes of memory space within the selected aperture of the configuration space.
 6. The method of claim 1, further comprising: generating a configuration read access packet using a split transaction protocol which includes (1) a configuration read request packet to initiate configuration read transactions, and (2) a configuration read completion packet to return configuration read data.
 7. The method of claim 6, further comprising: associating the configuration read completion packet with the corresponding configuration read request packet using a transaction number specified in the configuration packet header.
 8. A system comprising: a device having a configuration space which is divided into a plurality of configuration apertures; and a processor coupled to the device, the processing element to generate a configuration packet to access the configuration space of the device, wherein the configuration packet includes (1) first configuration information to select one of the apertures of the configuration space, and (2) second configuration information to address a specific location within the selected aperture.
 9. The system of claim 8, wherein the configuration packet includes a routing header and a configuration packet header.
 10. The system of claim 9, wherein a first value in a first control field of the routing header indicates that the packet is configuration space access.
 11. The system of claim 8, wherein the first configuration information is specified using 4-bit value to enable selection of up to sixteen configuration apertures of the device.
 12. The system of claim 8, wherein the second configuration information is specified using 32-bit addressing to address up to four gigabytes of memory space within the selected aperture of the configuration space.
 13. The system of claim 9, wherein the processor is configured to generate configuration read access packets using a split transaction protocol which includes (1) configuration read request packets to initiate configuration read transactions, and (2) configuration read completion packets to return configuration read data.
 14. The system of claim 13, wherein a configuration read completion packet is associated with a corresponding configuration read request packet by a transaction number specified in the configuration packet header.
 15. The system of claim 8, wherein the processor is configured to generate a configuration write packet having a routing header, a configuration packet header and a data payload.
 16. A configuration access mechanism comprising: a first logic to generate a configuration packet to access a configuration space which is divided into a plurality of apertures, wherein the configuration packet includes (1) first configuration information to select one of the apertures of the configuration space, and (2) second configuration information to address a specific location within the selected aperture; and a second logic to process a configuration packet received (1) to determine which one of the configuration apertures is being selected by the configuration packet and (2) to determine a specific address within the selected aperture being accessed by the configuration packet.
 17. The configuration access mechanism of claim 16, wherein the configuration packet includes a routing header and a configuration packet header, and wherein a first control field in the routing header having a first value indicates that the packet is configuration space access.
 18. The configuration access mechanism of claim 16, wherein the first configuration information is specified using a plurality of bits to enable selection of any one of the plurality of configuration apertures of the first device.
 19. The configuration access mechanism of claim 16, wherein the second configuration information is specified using 32-bit addressing.
 20. The configuration access mechanism of claim 16, wherein the first logic is configured to generate configuration read access packets using a split transaction protocol which includes (1) configuration read request packets to initiate configuration read transactions, and (2) configuration read completion packets to return configuration read data.
 21. The configuration access mechanism of claim 20, wherein a configuration read completion packet is associated with a corresponding configuration read request packet by a transaction number specified in the configuration packet header thereof.
 22. The configuration access mechanism of claim 19, wherein the first logic is configured to generate a configuration write packet having a routing header, a configuration packet header and a data payload. 